1. Field of the Invention
This invention relates to data processing systems. More particularly, this invention relates to the provision in a data processing system of a microcache for storing instruction data for a program loop.
2. Description of the Prior Art
It is known to provide a microcache within data processing systems. Such microcaches are described in the paper “Optimizations Enable By a Decoupled Front-End-Architecture” by Glenn Reinman et al. Microcaches are small, fast and low power storage mechanisms that can be used to store a small amount of instruction data, typically instruction data having a high probability of use. The provision of a microcache nevertheless represents an overhead in terms of circuit area and power.
It is also known within the field of microprocessors to provide hardware loop detection/prediction for various purposes. An example of such loop prediction is as discussed in “Path-based Hardware Loop Prediction” by Marcos R. de Alba et al. Such loop predictors can be usefully employed as part of the branch prediction mechanisms within microprocessors for predicting program flow and accordingly allowing high levels of instruction parallelism and instruction data prefetch.
The Xscale microprocessors produced by Intel Corporation incorporate a general array of cache line size buffers. These buffers can be used as store buffers, forwarding buffers, merge buffers, eviction buffers, linefill buffers, etc. Whenever a processing request arises that needs a buffer, then the next available general purpose buffer is allocated.